cshell/Makefile

42 lines
632 B
Makefile

# Sagi Dayan - Makefile
#
# compiler
CC=gcc
# compile arguments
CFLAGS+=-c -g -Wall
# linker flags
LDFLAGS+=
# libraries
LIBS+=
# our source files
SOURCES=main.c
# a macro to define the objects from sources
OBJECTS=$(SOURCES:.c=.o)
# executable name
EXECUTABLE=cshell
$(EXECUTABLE): $(OBJECTS)
@echo "Building target" $@ "..."
$(CC) $(LDFLAGS) $(OBJECTS) -o $@ $(LIBS)
@echo "Done!"
# a rule for generating object files given their c files
.c.o:
@echo "Compiling" $< "..."
$(CC) $(CFLAGS) $< -o $@
@echo "Done!"
clean:
@echo "Ceaning up *.o Files..."
rm -rf *s *o $(EXECUTABLE)
@echo "Done!"
.PHONY: all clean